Recently, various new technologies have been developed for improving data transferring speed of a double data rate (DDR) memory device. For instance, an off chip driver (OCD) calibration technology has been introduced to a specification of the DDR memory device by the JEDEC (Joint Electron Engineering Council) in order to adjust an impedance of a data output unit of the DDR memory device.
The optimum impedance of a data output driver for a current system is detected by measuring a voltage or a current which flows from an external circuit such as a chip set to the data output driver so that an impedance of the data output driver is adjusted to the optimum impedance. For this purpose, a DDR2 synchronous semiconductor memory device additionally includes an OCD control device for adjusting an impedance of the data output driver.
A termination impedance is needed for stably transferring a signal between circuits. If the termination impedance is not appropriately matched, a signal reflection error can occur, i.e., a transferred signal can be reflected back. However, if an external fixed resistor is provided, an appropriate matching may not be obtained due to aging of an integrated circuit, temperature variations or manufacturing process variations.
Therefore, a technology for adjusting the termination impedance has been developed in order to obtain an impedance match with an external reference impedance by controlling the number of turned-on transistors among a plurality of transistors connected in parallel.
FIG. 1 is a block diagram showing a conventional on-die termination (ODT) control device.
As shown, the conventional ODT control device includes an input buffer 10, a domain crossing block 20, a plurality of ODT blocks 30 and a plurality of terminal resistors 40.
The input buffer 10 performs a buffering operation of an ODT control signal ODT to output the buffered signal as an ODT command signal ODT_CMD.
The domain crossing block 20 receives the ODT command signal ODT_CMD to output an ODT enable signal ODT_EN to the plurality of ODT blocks 30 in synchronization with an output clock OCLK.
Accordingly, the plurality of ODT blocks 30 selectively connect the terminal resistors 40 to a power supply voltage terminal VDDQ or a ground voltage terminal VSSQ by using a plurality of switches SW1 and SW2 connected in parallel. As a result, it is possible to control a termination impedance of a semiconductor memory device.
The domain crossing block 20 generates the ODT enable signal ODT_EN in synchronization with the output clock OCLK which is uniform regardless of clock frequency. If the clock frequency of the semiconductor memory device grows shorter, it is difficult to control an active period of the ODT enable signal ODT_EN corresponding to the shortened clock frequency. As a result, the conventional ODT control device cannot accurately measure the termination impedance of the semiconductor memory device.